Demetrios Gavalas

• Developed RTL features for an FPGA image in SystemVerilog, including custom Ethernet PCS IP.
• Executed physical layer bring-up and characterization for low-latency transceivers.
• Wrote Python client code and framework to drive register configuration and packet streaming for FPGA image.

• Developed ASIC flow for a mixed-signal tapeout including SRAM using Synopsys DC, Cadence Innovus, and Siemens Calibre.
• Designed and prototyped RTL digital logic in Verilog and SystemVerilog to tape-out an ASIC for bird tagging.
• Managed tapeout logistics including coordinating I/O and packaging for several tapeouts and post-silicon test planning.
• Led effort to formally verify existing IP using Formal Verification tools, and tested silicon chip in hardware.
• Verified RTL blocks using CocoTB and PyMTL test benches and testing against software models of RTL blocks.
• Used Vivado to simulate ASIC design behavior on an FPGA for rigorous pre-tapeout testing.

• Designed and simulated a 6T Content-Addressable Memory bit cell and column using Cadence Virtuoso.
• Coordinated with a partner to partition and execute the custom layout of an SRAM-based CAM array and peripherals.
• Performed rigorous physical verification (DRC/LVS) and post-layout parasitic simulations to validate the design.
• Independently evaluated a novel compute-in-memory architecture under the advisement of Professor José Martínez.

• Analyzed timing of post-PNR FPGA designs and characterized delay for different levels of radiation exposure tolerance.
• Collaborated with engineers to design and verify components of the radar digital subsystem for VERITAS.
• Designed testbenches using CocoTB and Questa to simulate mission critical hardware alongside Python models.
• Developed program to automatically check design physical constraints against PCB netlists.
• Designed system for automated building and verification of FPGA designs for different target platforms.
• Deployed a local LLM model and implemented RAG pipeline to search internal documentation.

• Advising students on an interactive lab course including microfilm fabrication, AFM & SEM use components.
• Hosted office hours to help students with lab activities, problem sets, and general topics in nanoscience.

End-to-end, high performance (~200 FPS) Stereo Vision FPGA system, integrating analog camera and VGA peripherals, and host CPU software with hardware-accelerated image rectification, block matching, and smoothing.

Designed, laid out, and simulated a full-custom digital neuron, and simulated behavior as a classifier neural network.

Developed five stage multicore pipelined RISC processor in SystemVerilog with set associative caches, verified the design, and benchmarked its performance on different microbenchmarks.